1.Field of the Invention
The present invention relates generally to Sequential Access Memories (referred to as SAI hereinafter), and more particularly to the structure of an address pointer for selecting a row or a column of a memory cell array.
2. Description of the Background Art
Recently in the time of an information-oriented society, a signal processing technology particularly the technology of processing picture or video signals has become increasingly important. Conventionally this signal processing as done by an analog technology. However, recently due to the introduction of an integrated circuit it has been rapidly developed by utilizing a highly precise and more reliable digital technology.
When signal processing is done by using the digital technology, a semiconductor memory is necessary for temporarily storing a signal to delay the same signal. Particularly, concerning data representing one picture or video, data corresponding to each of the picture elements forming the picture are sequentially transmitted from a corner of the screen to be processed or his reason, an SAM is often used to delay those data.
FIG. 12 is a diagram schematically showing a structure of the main part of a conventional SAM. A memory cell array 1 includes a plurality of memory circuits 10 arranged in n rows and m columns. Each of the memory circuits 10 holds k bits of data. A plurality of row selecting lines 4 are provided corresponding to the rows of memory cell array 1, and a plurality of column selecting lines 5 are provided responsive to the columns of memory cell array 1.
A static type row address pointer 2a sequentially applies a plurality of row selecting signals Qr1-Qrn to a plurality of row selecting lines 4 for sequentially selecting one row of memory cell array 1. Row address pointer 2a includes a plurality of static type registers 30 for sequentially shifting data (row selecting signals) in synchronization with input clock signals, and even-numbered inverter circuits 31 for feeding back output signal of the last stage to the first stage of the registers 30. A inverter circuit 31 plays a role of a buffer for driving interconnection capacitance.
A static type column address pointer 3a sequentially applies column selecting signals Qc1-Qcm to column selecting lines 5 for sequentially selecting one column of memory cell array 1. As in the case of row address pointer 2a, column address pointer 3a includes a plurality of static type registers 30 for sequentially shifting data in synchronization with the input clock signals, and even numbered inverter circuits 31 for feeding back the output signal of the last stage to the first stage of the registers 30. The inverter circuits 31 also plays a role of a buffer for driving interconnection capacitance.
FIG. 13 is a timing chart showing the timing of the row selecting signals and the column selecting signals provided by address pointers 2a and 3a.
In the first cycle, a plurality of registers 30 included in row address pointer 2a sequentially shift data at a "H" level in response to the clock signals. Thereby, row selecting signals Qr1-Qrn sequentially attain a "H" level and m rows of memory cell array 1 are sequentially selected. In the first cycle, column selecting signal Qc1 is held at a "H" level by column address pointer 3a. As a result, memory circuit 10 of the first row and the first column, memory circuit 10 of the second row and the first column, . . . , and memory circuit 10 of the nth row and the first column are sequentially selected. Datum are written into and read from the selected memory circuits.
"H" level data held at the last stage register 30 in row address pointer 2a is shifted to the first stage register 30 through inverter circuits 31. Accordingly, in the second cycle, row selecting signals Qr1-Qrn sequentially rise to a "H" level. Thereby, the first row to the nth row of memory cell array 1 are sequentially selected. In the second cycle, column selecting signal Qc2 is held at a "H" level by column address pointer 3a. Thereby, the second column of memory cell array 1 is selected so that the memory circuit 10 of the first row and the second column, memory circuit 10 of the second row and the second column, . . . , and memory circuit 10 of the nth row and the second column are sequentially selected.
Similarly, in the mth cycle, memory circuit 10 of the first row and the mth column, memory circuit 10 of the second row and the mth column, . . . , and memory circuit 10 of the nth row and the mth column are sequentially selected. "H" level data held at the last stage register 30 in column address pointer 3a is shifted to the first stage register 30 through inverter circuits 31. As a result, after memory circuit 10 of the nth of the row and the mth column of memory cell array 1 is selected, memory circuit 10 of the first row and the first column is selected. Thereafter, the first cycle to the mth cycle as mentioned above will be repeated.
FIG. 14 is a circuit diagram showing one example of a structure of a static type register 30 included in row address pointer 2a and column address pointer 3a.
The register 30 includes P channel MOS transistors P1-P4, N channel MOS transistors N1-N4, and inverters G1-G4. Transistors P1 and N1 constitute a CMOS transmission gate T1, transistors P2 and N2 constitute a CMOS transmission gate T2, transistors P3 and N3 constitute a CMOS transmission gate T3, and transistors P4 and N4 constitute a CMOS transmission gate T4. A clock signal clkA is applied to transistors N1, P2, P3, and N4, and a clock signal CLKB is applied to transistors P1, N2, N3, and P4. As shown in FIG. 15, clock signals clkA and clkB constitute a double phase clock the "H" level periods of which do not occur at the same time.
A signal X.sub.j provided from the former stage register is applied to a node n1, and a signal X.sub.j+1 is provided to the next stage register from a node n3. Signal X.sub.j+1 is applied to memory cell array 1 as a row or column selecting signal Q.
When clock signal clkA is at a "L" level, and clock signal clkB is at a "H" level, transmission gates T2 and T3 turn on, and transmission gates T1 and T4 turn off. Consequently, the signal applied to a node n2 is latched to a latch circuit constituted by inverters G1 and G2, and transmission gate T3, and the signal is also provided as a signal X.sub.j+1 to node n3 through transmission gate T2 and inverters G3 and G4.
When clock signal clkA is at a "H" level, and clock signal clkB is at a "L" level, transmission gates T1 and T4 turn on, and transmission gates T2 and T3 turn off. Consequently, signal X.sub.j applied to node n1 is applied to node n2 through transmission gate T1, and inverters G1 and G2. Signal X.sub.j+1 of node n3 is latched to the latch circuit constituted by inverters G3 and G4, and transmission gate T4. In this manner, signal X.sub.j applied to node n1 in response to clock signals clkA and clkB is shifted to node n3.
Referring to FIG. 15 a time period in which clock signal ClkA attains "L" only once and attains "H" only once is referred to as one cycle T. Regarding the clock signal applied to registers 30 forming row address pointer 2a, the time when each of the row selecting signals Qr1-Qrn is at a "H" level corresponds to one cycle T. In connection with the clock signal applied to register 30 forming column address pointer 3a, the time when each of the column selecting signals Qc1-Qcm is at "H" level corresponds to one cycle T.
Furthermore, even when the operation timing of row address pointer 2a is replaced with the one of column address pointer 3a, the same operation as mentioned above will be carried out.
As mentioned above, in the conventional SAM, for the purpose of stably holding data (selection signals) a static type address pointer constituted by a plurality of static type registers 30 was employed in both row address pointer 2a and column address pointer 3a. For this reason, many transistors were used, and the occupation area of the address pointer on a semiconductor chip was increased. This was obstruction in obtaining an high integrated SAM.